Integrated circuit packaging has a significant effect on the appearance and function of end-user devices, from computers to cell phones to embedded processors. The packaging of IC devices should protect the integrated circuit die and allow coupling external to the IC die as needed. Integrated circuit (IC) packaging has evolved through multiple types of packaging technologies including, for example, system in package, package on package, chips first packaging, and so forth. In addition, it is becoming more common to commercially transfer or sell IC devices that have only been partially packaged. These partially packaged IC devices can then be optionally combined with other circuit devices and packaged in a final form to produce the desired final circuit.
In chips-first packaging, the IC die or dies are at least partially encapsulated in a molding compound. The IC die or dies are then mounted to an inert substrate with their active surfaces face up. Interconnect circuitry is then built above the active surface of the IC dies. The interconnect circuitry is formed to the IC chip as an integral part of the processing, thus eliminating the need for wire bonds, tape-automated bonds (TABs), or solder bumps. Furthermore, such a packaging technique can support high density interconnect routing, can minimize package area by reducing the distance between die contact and package ball grid array or pads, can improve power efficiency, and so forth.
FIG. 1 shows a side view of a prior art integrated circuit (IC) die package 20 which may be packaged in accordance with a chips-first packaging technique. IC die package 20 includes an IC die 22 largely encapsulated in a molding compound 24. Following the encapsulation of IC die 22 in molding compound 24, an active surface 26 of IC die 22 is electrically coupled with an interconnect layer 28. Interconnect layer 28 may include one or more levels of interconnect and may be formed using a variety of processes such as, for example, high density interconnect build-up, lamination, thin film processing, and so forth. IC die 22 may be a power amplifier semiconductor device. Arrows 30 represent the heat generated by IC die 22 during operation.
Power amplifier semiconductor devices are discrete devices or integrated circuits intended for high current or high voltage applications. Due to relatively large current conduction, all power semiconductor devices heat up. Unfortunately, semiconductors do not perform well and/or can fail at elevated temperatures. Therefore, a power semiconductor device needs to be cooled by removing that heat continuously. Chips-first packaging of some power semiconductor devices has been problematic because the molding compound that encapsulates such a power amplifier IC die does not effectively dissipate heat generated by the power amplifier semiconductor device. This trapped heat can cause poor performance and/or failure of the power amplifier semiconductor device.
Additionally, radio frequency (RF) semiconductor design calls for the effective grounding of such RF devices. The encapsulation of an RF device in molding compound during chips-first packaging can complicate the inclusion of effective grounding in such a device.
Accordingly, what is needed is a method for effectively packaging IC dies with improved heat dissipation capability and/or effective grounding capability that can be readily implemented in existing packaging methodologies while concurrently minimizing packaging thickness.